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Low Power Asic Implementation of LDPC Decoder

D. Venkatesan*, B. Sunil, B. Ajay Reddy and K. Jagannadha Naidu

In this paper, a low power ASIC implementation of LDPC decoder architecture is presented. The proposed LDPC decoder works based on the principle of min-sum algorithm The proposed LDPC decoder requires limited amount of hard ware resources because of the property of reduced number of iterations in min-sum algorithm because min-sum algorithm is an iteration based error corrector so that we can use the same hardware with limited hardware and the error corrected part is not checked and modified so that we can utilize that hardware for the error correction of other parts or turnoff that so that power can be saved and the iterations required for it also decreases when compared to other decoding algorithms like sumproduct and layered decoding algorithms. The other design achieves better Bit Error Rate (BER) performance. After performing synthesis the total area occupied by current design is 1417 (μM2) and the total power is given as 13.726 (nW). The frequency of current design is obtained as 2.5 MHz. After applying power optimization techniques the total power consumed by current design is reduced by 99.99% when compared to existing design