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Design of High Speed Optimized Vedic Multiplication Techniques

D. Rajasekar* and E. Anbalagan

This paper proposed “The design of ALU using the techniques of Ancient Indian Vedic Calculation” that has been modified into improve performance. The speed of Arithmetic and Logic Unit depends mostly on multiplier. The Vedic Calculation is the ancient system of mathematics which has been a unique techniques of calculation based on 16 Sootra. The work has proved and compared the efficiency of Urdhva-Triyagbhyam vedic method for multiplications which strikes a difference in the actual process of multiplications itself. It generate parallel generation of intermediate products, eliminates unwanted multiplications steps with 0’s and scaled to MSB bit levels using Karatsuba algorithm (Divide and Conqure) with the compatibility to different data types. Geometric progression accumulate is an extensible block using in the Vedic multipliers module plays an important role in computing, especially DSP. The coding is done in verilog Hardware Description Language and the Field Program Gated Array syntax is done using Xilinix Spartan library. The result show that Vedic multiplications is efficient in terms of area and velocity compared to conventional multiplication.